5-Stage Pipelined RISC-V Processor
Implemented a RV32I processor in Verilog with full data forwarding and hazard detection. Synthesized on Artix-7 FPGA at 85 MHz. Verified via Verilator compliance suite.
> Systems-oriented Software Engineer @ UofT
Specializing in Computer Architecture, Kernel Development, and AI Infrastructure.
Systems-oriented software engineer with a strong interest in computer architecture, device drivers, and AI infrastructure. Experienced in low-level C/Assembly, kernel development, and processor design. Passionate about bridging the gap between silicon and software.
B.Sc. in Software Engineering
RELEVANT_COURSEWORK: Computer Org, OS, Algorithms, Computer Networks.
Research Intern — Seed Team
AI Engineer, Agent Development
Implemented a RV32I processor in Verilog with full data forwarding and hazard detection. Synthesized on Artix-7 FPGA at 85 MHz. Verified via Verilator compliance suite.
Loadable kernel module with ioctl interfaces and kernel-space ring buffer. Utilized mutex/spinlock for concurrency. Debugged via KGDB/QEMU and ftrace.
Built a framebuffer rendering engine on 32-bit MIPS. Directly managed CPU registers and MMIO. Optimized via branch delay slot utilization and register allocation.
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