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> Systems-oriented Software Engineer @ UofT

Specializing in Computer Architecture, Kernel Development, and AI Infrastructure.

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01. ABOUT_ME

Systems-oriented software engineer with a strong interest in computer architecture, device drivers, and AI infrastructure. Experienced in low-level C/Assembly, kernel development, and processor design. Passionate about bridging the gap between silicon and software.

University of Toronto

B.Sc. in Software Engineering

GPA: 3.7/4.0 2023 – 2027

RELEVANT_COURSEWORK: Computer Org, OS, Algorithms, Computer Networks.

02. PROFESSIONAL_EXPERIENCE

ByteDance

Research Intern — Seed Team

Sep – Dec 2025 Beijing, China
  • Developed a Vision-Language-Action (VLA) model integrating 3D geometry with semantic understanding for robotics.
  • Engineered a multimodal fusion pipeline: utilized MapAnything for 2D-to-3D reconstruction and combined spatial coordinates with SigLIP embeddings.
  • Designed a generative action head using Flow Matching to generate precise continuous action tokens.

China Unicom

AI Engineer, Agent Development

May – Aug 2025 Beijing, China
  • Architected an autonomous agent system routing diverse data to a hybrid MongoDB/PostgreSQL storage layer.
  • Built a dynamic RAG engine on vectorized data for natural language querying and real-time analytics generation.
  • Implemented the Model Context Protocol (MCP) for modular agent skills and autonomous schema evolution.

03. FORGED_IN_CODE

PRJ_01
STABLE

5-Stage Pipelined RISC-V Processor

Implemented a RV32I processor in Verilog with full data forwarding and hazard detection. Synthesized on Artix-7 FPGA at 85 MHz. Verified via Verilator compliance suite.

Verilog Verilator Vivado FPGA
PRJ_02
KERNEL

Linux Kernel Character Driver

Loadable kernel module with ioctl interfaces and kernel-space ring buffer. Utilized mutex/spinlock for concurrency. Debugged via KGDB/QEMU and ftrace.

C Kernel API QEMU GDB
PRJ_03
BARE_METAL

Bare-Metal MIPS Graphics Engine

Built a framebuffer rendering engine on 32-bit MIPS. Directly managed CPU registers and MMIO. Optimized via branch delay slot utilization and register allocation.

MIPS Assembly C QEMU Systems

04. TECH_STACK

root@luyuange: /etc/skills

LANGUAGES

C/C++ Python Rust Go Verilog Assembly Java

SYSTEMS_&_HARDWARE

Linux Kernel RISC-V/ARM FPGA QEMU CUDA Cache/Pipeline

INFRA_&_AI

Docker/K8s PyTorch vLLM RAG LangGraph PostgreSQL

05. ESTABLISH_CONNECTION

guest@luyuange:~$